1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and, more particularly, to a multi-column decoder stress test circuit that can reduce the test time for a semiconductor memory.
2. Related Art
Presently, there are limited test capabilities for testing a semiconductor memory once it has been packaged. However, a burn-in stress test for a highly integrated semiconductor memory device is time consuming. This in turn increases both the amount of time required to manufacture the memory and increases the manufacturing. Although a burn-in stress test is generally performed in a package state (hereinafter, referred to as “package burn-in stress test”), research for a wafer burn-in stress test, in which the stress test is performed while the memory is in a wafer state, has been actively conducted to reduce the burn-in stress time. Such a wafer burn-in stress test may be performed within a short period of time, as compared with the package burn-in stress test. This is because a relatively long time is necessary to install a package-type semiconductor memory device in a burn-in stress system. Additionally, since the package-type semiconductor memory device is manually installed in the burn-in stress system, a labor force is required. Further, in the package burn-in stress test, the number of packages which simultaneously undergo the burn-in stress test is limited. In contrast, since the wafer burn-in stress test can be performed with respect to a plurality of sheets of wafers having several dies, the wafer burn-in stress test has an advantage in terms of test efficiency. As described above, since the wafer burn-in stress test can be performed within a short period of time as compared with the conventional package burn-in stress test, the wafer burn-in stress test is extensively used.
FIG. 1 is a block diagram illustrating a column decoder stress test circuit 100 used in a conventional wafer burn-in test. Referring to FIG. 1, the column decoder stress test circuit 100, according to a conventional circuit, includes first to third predecoders 10 to 30, an even decoder 40, and an odd decoder 50. The first to third predecoders 10 to 30 receive and decode column addresses ‘BYA<1:2>’, ‘BYA<3:5>’, and ‘BYA<6:8>’, respectively. The use of several predecoders such as the first to third predecoders 10 to 30 is necessary to reduce the number of gates of the even decoder 40 and the odd decoder 50.
The even decoder 40 receives outputs from the first to third predecoders 10 to 30 and outputs the even column selection signals ‘Yi<0>’, ‘Yi<2>’, ‘Yi<4>’, ‘Yi<6>’, . . . , and ‘Yi<2n>’. The odd decoder 50 receives the outputs from the first to third predecoders 10 to 30 and outputs the odd column selection signals ‘Yi<1>’, ‘Yi<3>’, ‘Yi<5>’, ‘Yi<7>’, . . . , and ‘Yi<2n+1>’. Accordingly, the even column selection signals ‘Yi<0>’, ‘Yi<2>’, ‘Yi<4>’, ‘Yi<6>’, . . . , and ‘Yi<2n>’ are arranged adjacent to each other, and the odd column selection signals ‘Yi<1>’, ‘Yi<3>’, ‘Yi<5>’, ‘Yi<7>’, . . . , and ‘Yi<2n+1>’ are also arranged in adjacent to each other.
Referring to FIG. 2, the first predecoder 10 includes a plurality of NOR gates and a plurality of AND gates. In detail, the first predecoder 10 includes a plurality of NOR gates to receive and decode the column addresses ‘BYA<1>’ and ‘BYA<2>’ and a plurality of AND gates to receive outputs of the NOR gates and an active pulse ‘AYP16’. The active pulse ‘AYP16’ is a pulse signal, and occurs by the number of burst lengths (BLs) in a write or read operation. Accordingly, as shown in FIG. 2, the first predecoder 10 receives the two column addresses ‘BYA<1:2>’ to output four signals ‘YA12<0:3>’.
Referring to FIG. 3, the second predecoder 20 includes a plurality of NOR gates and a plurality of AND gates. In detail, the second predecoder 20 includes a plurality of NOR gates and a plurality of AND gates to receive and decode the column addresses BYA<3:5>. Accordingly, as shown in FIG. 3, the second predecoder 20 receives the three column addresses ‘BYA<3:5>’ and outputs eight signals ‘YA345<0:7>’.
Referring to FIG. 4, the third predecoder 30 includes a plurality of NOR gates and a plurality of AND gates. In detail, the third predecoder 30 includes a plurality of NOR gates and a plurality of AND gates to receive and decode the column addresses ‘BYA<6:8>’. Accordingly, as shown in FIG. 4, the third predecoder 30 receives the three column addresses ‘BYA<6:8>’ and outputs eight signals ‘YA678<9:7>’. Accordingly, the even decoder 40 and the odd decoder 50 receive the outputs of the first to third predecoders 10 to 30 and output the 256 column selection signals ‘Yi<0>’, . . . , ‘Yi<255>’.
Accordingly, a conventional column decoder stress test circuit enables only the column selection signals corresponding to the information about the column addresses and disables other column selection signals so as to perform a test. Thus, in a conventional wafer burn-in test, only one column selection signal is enabled, and therefore the wafer burn-in test is performed relative to one column line. Additionally, the wafer burn-in test may not be performed, or the wafer burn-in test is performed by enabling only one column selection signal. Therefore, it is difficult to provide sufficient stress to all column lines during a wafer burn-in test. As a result, when the wafer burn-in test is performed according to the related art, an exact test result cannot be obtained in a test such as early failure rate (EFR), a high temperature operating life (HTOL), or a low temperature operating life (LTOL), which is a kind of a package test or a reliability test. Accordingly, contact defect may occur or function fail or DC current fail (IDD fail) may occur through a line bridge.